High sheet resistance (R.sub.S) of buried bit lines in a ROM becomes more severe when the cell dimension shrinks as memory density increases. When the cell dimension shrinks, the bit line width also shrinks and the bit line sheet resistance increases. In addition, the punch through voltage between adjacent bit lines becomes unacceptably low.
FIG. 1 illustrates a buried bit line ROM 10. The ROM 10 comprises a P-type silicon substrate 11. A plurality of N.sup.+ -type buried bit lines 12 are formed in the ROM 10. Each bit line has a width W and the spacing between adjacent bit lines is S. A plurality of polysilicon word lines 14 are also formed on the surface of the substrate 11. The ROM 10 comprises a plurality of cells. One such cell 30 is delineated in FIG. 1 and shown in a cross-section view taken along the line AA' in FIG. 2.
As shown in FIG. 2, the cell 30 comprises two adjacent buried bit lines 12 which form source and drain regions for the cell. A channel 22 of length S is formed between the two bit lines in the cell 30. A gate oxide layer 16 is formed on top of the substrate 11. The oxide layer is thick at portions 18 which are located above the bit lines 12 and thin at portion 20 located over the channel 22. A polysilicon word line 24 is formed over the gate oxide layer 16.
As indicated above, when the bit line width W is too small, the bit line sheet resistance is unacceptably high. In addition, when the bit line spacing S is too small, the punch through voltage between adjacent bit lines is unacceptably low.
It is an object of the present invention to provide a buried bit line structure and a method for making a buried bit line structure which eliminates the sheet resistance and punch through voltage problems in high density buried bit line ROMs with small bit line width and small bit line spacing.